SAKTHIVEL
CONTACT ME
Open to Summer 2026 Internships

Hey. I'm Sakthivel,

AN FPGA & Hardware ENGINEER

EEE student at Imperial College London — building low-latency systems and hardware accelerators for quantitative finance.

VIEW PROJECTS GITHUB
Sakthivel Balaji Perumal
2nd Year at Imperial
1540 SAT Score
1st Place Makeathon
CSWP Certified

FPGA DEVELOPMENT

Verilog/VHDL design, synthesis, and implementation for high-frequency trading applications.

LOW-LATENCY SYSTEMS

Hardware accelerators optimised for nanosecond-level performance in trading systems.

QUANTITATIVE ANALYSIS

Data-driven approach combining mathematical rigour with Python and C++ implementation.

HARDWARE PROTOTYPING

CAD design (CSWP certified), PCB layout, and rapid prototyping for embedded systems.

TECH STACK

Tools and technologies I work with daily.

Verilog
VHDL
SystemVerilog
Python
C++
MATLAB
Vivado
SolidWorks

BUILDING LOW-LATENCY
HARDWARE FOR
QUANTITATIVE FINANCE

I'm an intellectually curious MEng Electrical and Electronic Engineering student at Imperial College London with a drive to solve the hardest problems at the intersection of technology and finance.

Combining a rigorous mathematical foundation with strong programming skills in Python and C++, I take a data-driven approach to quantitative challenges. I thrive in collaborative, fast-paced environments and am eager to apply my entrepreneurial spirit to learn from daily feedback in competitive markets.

My focus is on FPGA development for ultra-low-latency trading systems — where every nanosecond counts and hardware design directly impacts market performance.

PROJECTS

Explore my recent FPGA and hardware projects.

Verilog

fpga-order-book

Hardware-accelerated limit order book implementation achieving sub-microsecond latency for market data processing.

⭐ 24 🔀 8
SystemVerilog

market-data-parser

FPGA-based market data feed handler with hardware parsing for ITCH/OUCH protocols.

⭐ 18 🔀 5
Python

hft-backtester

Event-driven backtesting framework for high-frequency trading strategies with realistic latency simulation.

⭐ 42 🔀 12
C++

ultra-low-latency-network

Kernel-bypass networking stack using DPDK for sub-microsecond packet processing.

⭐ 31 🔀 9
VHDL

pipelined-fpu

Fully pipelined IEEE 754 floating-point unit optimised for high-throughput financial calculations.

⭐ 15 🔀 4
Verilog

ethernet-mac-10g

10 Gigabit Ethernet MAC implementation with hardware timestamping for latency measurement.

⭐ 27 🔀 7

EXPERIENCE

Oct 2025

NASA SpaceApps Hackathon

NASA · Remote

Participated in the global NASA SpaceApps challenge, developing innovative solutions for space exploration challenges using hardware and software integration.

Jul 2025

1st Place — CGCU Makeathon

Imperial College London

Led a team of 4 to design and manufacture a prototype specialised motorbike for unexplored planetary terrain in a 48-hour challenge. Featured energy harvesting from radiation and protective shielding systems.

Jul 2022

Engineering Intern

Petrofac · Woking

Week-long work experience across different engineering disciplines. Gained exposure to how engineers create real-world solutions to complex client problems in the energy sector.

EDUCATION

Imperial College London

MEng Electrical and Electronic Engineering

Sep 2024 — Jun 2028

Focusing on digital systems, FPGA design, signal processing, and embedded systems. Active member of EEE society and CGCU.

Queen Elizabeth's School, Barnet

A-Levels: Maths, Further Maths, Physics

Sep 2017 — Jul 2024

SAT: 1540 (Maths: 800/800) · HPQ: A* · CSWP & CSWA Certified in SolidWorks

Let's Build Something Fast

I'm actively seeking FPGA engineering internships for Summer 2026 at quantitative trading firms. If you're working on low-latency systems and looking for a driven engineer, let's connect.

LinkedIn GitHub Email